DocumentCode
2663022
Title
Minimal forbidden minor characterization of planar partial 3-trees and application to circuit layout
Author
Dai, Wayne Wei-Ming ; Sato, Masao
Author_Institution
Comput. Eng. Board of Studies, California Univ., Santa Cruz, CA, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
2677
Abstract
All the minimal forbidden minors for planar partial 3-trees are derived K -trees and partial K -trees, theorems on partial K -trees, and theorems on partial 3-trees are discussed. Graph-theoretic definitions are discussed, and application to circuit layout is analyzed
Keywords
circuit layout; network topology; trees (mathematics); K-trees; circuit layout; graph-theoretic definitions; minimal forbidden minors; partial K-trees; planar partial 3-trees; Application software; Bridges; Circuits; Particle separators; Routing; Steiner trees;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112560
Filename
112560
Link To Document