Title :
FPGA implementation of real-time image convolutions with three level of memory hierarchy
Author :
Jiang, Hongtu ; Owall, Viktor
Author_Institution :
Dept. of Electrosci., Lund Univ., Sweden
Abstract :
In this paper, a customized image convolution processor with three level memory hierarchy is implemented on Xilinx VirtexE FPGAs. Due to its fully pipelined datapath for calculations and streamlined data flow architecture, the processor has the performance close to that of TI highest performance C64x processor at less than 1/8 of the clock frequency with substantial I/O bandwidth reductions. Furthermore, potential power savings are envisioned in future ASIC implementations by meaningful memory hierarchy explorations. In addition, a dedicated controller composed of Finite State Machine with incremental branch optimization architecture is developed to control all the operations in calculations and data transfer.
Keywords :
control system synthesis; field programmable gate arrays; finite state machines; image processing; memory architecture; ASIC implementation; C64x processor; FPGA implementation; I/O bandwidth reduction; Xilinx VirtexE FPGA; application specific integrated circuits; clock frequency; control system synthesis; data transfer; field programmable gate arrays; finite state machine; image convolution processor; incremental branch optimization; memory hierarchy exploration; pipelined datapath; potential power savings; real time image convolutions; streamlined data flow; Application specific integrated circuits; Clocks; Digital signal processing; Field programmable gate arrays; Filtering; Frequency; Hardware; Kernel; Libraries; Streaming media;
Conference_Titel :
Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on
Print_ISBN :
0-7803-8320-6
DOI :
10.1109/FPT.2003.1275793
