Resource allocation and code generation for pointer based pipelined DSP multiprocessors

Author

Kim, B.M. ; Barnwell, T.P., III

Author_Institution

Sch. of Electr. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

1990

fDate

1-3 May 1990

Firstpage

2685

Abstract

A multiprocessor compiler that automatically produces efficient code for synchronous multiprocessors based on digital signal processing (DSP) chips is presented. A code-scheduling technique that is based on an extended list scheduler with partial backtracking is developed. Resource allocations are performed along with the backtracking code scheduling for best results. The scheduler is suboptimal, and relies on several heuristics. The scheduler is shown to be quite efficient in generating codes for many DSP algorithms and for several single-chip DSP processors

Keywords

digital signal processing chips; pipeline processing; program compilers; resource allocation; backtracking code scheduling; code generation; code-scheduling technique; extended list scheduler; multiprocessor compiler; partial backtracking; pointer based pipelined DSP multiprocessors; resource allocations; single-chip DSP processors; suboptimal; synchronous multiprocessors; Arithmetic; Digital signal processing; Digital signal processing chips; Multiprocessing systems; Parallel processing; Processor scheduling; Registers; Resource management; Scheduling algorithm; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112562

Filename

112562