DocumentCode
2663059
Title
Performance analysis of asynchronous hierarchical-bus multiprocessor systems using closed queuing network models
Author
Mahmud, Syed Masud
Author_Institution
Dept. of Electr. & Comput. Eng., Wayne State Univ., Detroit, MI, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
2689
Abstract
The performance of asynchronous packet-switched hierarchical and multibus multiprocessor systems is analyzed. The performance is measured using both analytical and simulation models. The performance measured from the analytical model is found to be very close to the performance measured from the simulation model. The performance of a hierarchical bus system is found to be far better than that of an equivalent multiple-bus system for nonuniform memory reference systems. The results show that when multiple parallel buses or high-speed buses are used at the higher levels, a hierarchical bus system becomes as good as a multiple bus system (with the same number of buses) for general-purpose computations, although the cost of the hierarchical bus system is significantly lower than the cost of a multiple bus system
Keywords
computer interfaces; hierarchical systems; multiprocessor interconnection networks; packet switching; queueing theory; analytical model; asynchronous hierarchical-bus multiprocessor systems; closed queuing network models; cost; general-purpose computations; hierarchical bus system; high-speed buses; multibus multiprocessor systems; multiple parallel buses; multiple-bus system; nonuniform memory reference systems; packet switched hierarchical systems; simulation models; Analytical models; Bandwidth; Computer networks; Costs; Electric variables measurement; Multiprocessing systems; Packet switching; Performance analysis; Queueing analysis; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112563
Filename
112563
Link To Document