Title :
Defect analysis, test generation and fault simulation for gate oxide shorts in CMOS ICs
Author :
Syed, Suhail I. ; Wu, David M.
Author_Institution :
Florida Inst. of Technol., Melbourne, FL, USA
Abstract :
The correlation between gate oxide shorts (GOSs) and delay defects is investigated. Results show that both GOSs and small delay defects can be detected by static IDD tests. Generalized rules for GOS test generation and fault simulation are developed
Keywords :
CMOS integrated circuits; digital integrated circuits; integrated circuit testing; logic testing; CMOS ICs; defect analysis; delay defects; digital ICs; fault analysis; fault simulation; gate oxide shorts; gate propagation delay increase; static IDD tests; test generation; Analytical models; CMOS integrated circuits; CMOS logic circuits; Circuit faults; Circuit testing; Current measurement; Logic testing; Manufacturing; Power system reliability; Propagation delay;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112567
