Title :
A critical hazard detection scheme for semi-custom VLSI
Author :
Fujimoto, Tetsuya ; Noda, Hiroaki ; Kambe, Takashi
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Abstract :
A timing-verification method for practical use is presented. The scheme can be applied to circuits which involve complicated timing behaviors. Conventional methods are discussed. The definitions of several terms are given. A detailed description of the approach is presented. Experimental results for two digital circuits implemented on gate-array VLSIs are presented
Keywords :
VLSI; hazards and race conditions; logic CAD; logic arrays; asynchronous timing behaviour; complicated timing behaviors; critical hazard detection scheme; definitions; digital circuits; fault analysis; gate-array VLSIs; semi-custom VLSI; timing-verification method; Circuit simulation; Circuit testing; Clocks; Computer errors; Computer science; Digital circuits; Hazards; Logic circuits; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112568
