Title :
IC spot-defect and fault semantics-a unified framework
Author :
De Gyvez, Jose Pineda ; Jess, J.A.G.
Author_Institution :
Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
Abstract :
A theoretical framework to model spot defects with their related faults in any IC technology is presented. The defect models are unintended geometrical variations introduced in the shape of the patterns of the IC. The transcendence of a defect is determined by the impact that it has at several levels of abstractions. This impact is called a fault. The framework is a mathematical construction which encompasses a hierarchical fault modeling that avoids irrelevant information at every level of abstraction. The framework includes consistency requirements on fault modeling which can be used to analyze the origins and reasons of malfunctions in production chips
Keywords :
MOS integrated circuits; failure analysis; fault location; lithography; IC spot-defect; IC technology; consistency requirements; failure analysis; fault analysis; fault semantics; hierarchical fault modeling; levels of abstractions; mathematical construction; production chips; reasons of malfunctions; related faults; spot defects model; theoretical framework; unified framework; unintended geometrical variations; Chemical technology; Circuit faults; Crystalline materials; Integrated circuit modeling; Integrated circuit technology; Mathematical model; Microelectronics; Shape; Silicon; Solid modeling;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112569
