A top-down built-in self-test design in VLSI testing

A top-down design of test generation and response analysis for built-in self-test (BIST) is proposed. The design procedure is computationally efficient for test generation, and produces test generation circuitry with low hardware overhead. The effectiveness of the approach is demonstrated by detailed comparisons of the results with those obtained with existing techniques. For response analysis, a delay redundancy check is proposed to improve the failure rate of a vertical and horizontal redundancy check fault-detection scheme. In combination with the two-signature scheme, the frequency of aliasing is reduced to one in 2⁴ⁿ for an n-input, m-output circuit under test, where 2ⁿ>m