A testing methodology for large scale hybrid VLSI

Author

Welles, Kenneth, II ; Hartley, Richard ; Chatterjee, Abhijit ; Delano, Paul ; Hartman, Michael

Author_Institution

General Electric CRD, Schenectady, NY, USA

fYear

1990

fDate

1-3 May 1990

Firstpage

2724

Abstract

A test methodology for large systems-on-a-chip designed by the Discretionary Interconnect One Day Electronic System (DIODES) system for the rapid prototyping of digital signal processing (DSP) electronic systems is discussed. DIODES is based on the concept of building a library of chips that implement a set of operators used in DSP algorithms, and using these chips to implement DSP algorithms by implanting them on an alumina substrate and interconnecting them appropriately to realize the desired functionality. Test hardware capabilities are discussed. A description of test circuitry is given. The test methodology is compared with boundary scan

Keywords

VLSI; hybrid integrated circuits; integrated circuit testing; Al₂O₃ substrate; DIODES; DSP systems prototyping; Discretionary Interconnect One Day Electronic System; boundary scan; design for testability; fault analysis; large scale hybrid VLSI; large systems-on-a-chip; library of chips; rapid prototyping; test methodology; testing methodology; Circuit testing; Digital signal processing chips; Diodes; Electronic equipment testing; Integrated circuit interconnections; Large-scale systems; Signal design; Signal processing algorithms; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112572

Filename

112572