Title :
An efficient algorithm for constructing systolic arrays from VLSI/WSI containing faulty elements
Author_Institution :
Dept. of Math. & Inf. Sci., Ryukoku Univ., Siga, Japan
Abstract :
An efficient polynomial-order algorithm for the compensation path finding problem which has been previously reduced to an NP-complete problem is given. The algorithm uses four queues of faulty processing elements (PEs) obtained by sorting faulty PEs with respect to their locations in the array, and successively finds compensation paths for the faulty PEs at the exits of the queues. A branching scheme is used to search for compensation paths depending on the relative positions of the faulty PEs at the exits of the queues. The time complexity of the algorithm is O(n3) in the worst case, where n is the number of faulty PEs. The space complexity of the algorithm is O(n)
Keywords :
VLSI; computational complexity; systolic arrays; NP-complete problem; VLSI; VLSI/WSI containing faulty elements; WSI; branching scheme; compensation path finding problem; constructing systolic arrays; efficient polynomial-order algorithm; fault analysis; four queues of faulty processing elements; search for compensation paths; sorting faulty PEs; space complexity; successively finds compensation paths; time complexity; Circuit faults; Information science; Integrated circuit manufacture; Integrated circuit technology; Mathematics; Sorting; Space technology; Switches; Systolic arrays; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112575