Restructure algorithm for testable PLA

Author

Hwang, Gwo-Haur ; Shen, Wen-Zen

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan

fYear

1990

fDate

1-3 May 1990

Firstpage

2740

Abstract

A programmable logic array (PLA) restructure algorithm which enhances the testability of PLAs is presented. This algorithm transforms the input logic function to a more testable form, and gets a higher testability PLA. The PLA is mapped into a testable structure by adding less extra hardware. In order to get a more testable PLA, the following two strategies are used in the restructure algorithm: (1) Give up the prime cubes. (2) If necessary, partition the more untestable cubes. An efficient program has been implemented in C on a SUN workstation. For 40 benchmark examples, the average overhead reduction is shown to be about 37%

Keywords

integrated circuit testing; logic CAD; logic arrays; logic testing; C language; SUN workstation; benchmark examples; design for testability; fault analysis; higher testability PLA; highly testable PLA; input logic function transformation; overhead reduction; partitioning; prime cubes; programmable logic array; restructure algorithm; strategies; testability enhancement; testable PLA; untestable cubes; Benchmark testing; Circuit testing; Hardware; Logic design; Logic functions; Logic testing; Partitioning algorithms; Programmable logic arrays; Sequential circuits; Sun;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112576

Filename

112576