Title :
Fault tolerant memory designs for improved yield and reliability
Author_Institution :
Dept. of Electr. & Comput. Eng., West Virginia Univ., VA, USA
Abstract :
Fault tolerant memory designs aimed at providing high fault coverage are proposed. Reconfiguration strategies for single cell failure, multiple cell failures, single row failure, multiple row failures, single column failure, multiple column failures, and decoder failures are presented. The effect of reconfiguration on the yield and reliability of the memory design is analyzed. The designs are optimized for minimal area overhead. A significant improvement in yield and reliability is observed when an optimal number of redundant spares are used
Keywords :
DRAM chips; MOS integrated circuits; VLSI; fault tolerant computing; integrated memory circuits; reliability; 1 Mbit; DRAMs; MOS ICs; decoder failures; effect of reconfiguration; fault analysis; fault tolerant memory design; high fault coverage; minimal area overhead; multiple cell failures; multiple column failures; multiple row failures; optimal number of redundant spares; reconfiguration strategies; reliability enhancement; single cell failure; single column failure; single row failure; yield enhancement; Circuit faults; Decoding; Error correction; Error correction codes; Fault detection; Fault tolerance; Hardware; Registers; Strontium; Testing;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112577
