DocumentCode
2663342
Title
Design of robust-fault-tolerant arithmetic circuits and their application
Author
Kasuga, Takeshi ; Kameyama, Michitaka ; Kiguchi, Takanori
Author_Institution
Fukushima Nat. Coll. of Technol., Iwaki, Japan
fYear
1990
fDate
1-3 May 1990
Firstpage
2748
Abstract
Robust-fault-tolerant arithmetic circuits for a highly safe digital system are proposed. Two kinds of robust-fault-tolerant arithmetic circuits based on distributed coding are designed. One is a robust-fault-tolerant adder, and the other is a robust-fault-tolerant multiplier. It is shown in an experiment of robot control that the safety of the proposed arithmetic circuits is superior to that of the ordinary binary arithmetic circuits
Keywords
adders; digital arithmetic; fault tolerant computing; industrial robots; multiplying circuits; application; distributed coding; fault analysis; highly safe digital system; robot control; robust-fault-tolerant adder; robust-fault-tolerant arithmetic circuits; robust-fault-tolerant multiplier; safety; Adders; Arithmetic; Bidirectional control; Counting circuits; Equations; Pulse generation; Robust control; Robustness; Shift registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112578
Filename
112578
Link To Document