DocumentCode
2663358
Title
A new design to prevent fault equivalence in PLAs
Author
Liu, B.D. ; Shaw, G.T.
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
1990
fDate
1-3 May 1990
Firstpage
2752
Abstract
The fault equivalence problem in programmable logic arrays (PLAs) is introduced. Some design rules are proposed. Based on the pseudoexhaustive testable PLA structure, a diagnosis algorithm was developed and implemented on a SUN 3/110 workstation in C language. Experimental results show that this design and the algorithm are quite efficient for PLA fault diagnosis
Keywords
VLSI; integrated circuit testing; logic CAD; logic arrays; logic testing; C language; PLA fault diagnosis; PLAs; SUN 3/110 workstation; design rules; diagnosis algorithm; fault analysis; fault equivalence prevention; programmable logic arrays; pseudoexhaustive testable PLA structure; Circuit faults; Circuit testing; Counting circuits; Decoding; Electrical fault detection; Fault detection; Fault diagnosis; Programmable logic arrays; Shift registers; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112579
Filename
112579
Link To Document