Design and Implementation of a Real-Time JNAM-CFAR Processor in FPGA

In this paper, JNAM-CFAR detector as a sub-optimum radar detector for marine heterogeneous environments is introduced. Moreover the implementation of this detector using XILINX System Generator software is presented and some features such as cost, flexibility and speed have improved in comparison with the customary detectors. Meanwhile we have estimated the required hardware for the implementation of the JNAM detector using SPARTAN 3 FPGA chips (3s400pq208-5). A comparison between CA-CFAR and the JNAM detector in implementation view point have been done and the results illustrated good performance of the proposed detector.