Title :
Improving timing characteristics through Semi-Random Net Reordering
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Sharjah, Sharjah, United Arab Emirates
Abstract :
This work discusses the Semi-Random Net Reordering (SRNR) technique as a means to improve signal integrity and predictability of timing characteristics for wide signal busses. SRNR is able to reduce induced noise, signal propagation delay, signal transition speed, and their variations amongst the different wires comprising the bus. SRNR produces a faster routing structure that is more uniformly behaved. It has the advantage of zero cost and applicability under the strictest routing methodologies.
Keywords :
delay circuits; high-speed integrated circuits; integrated circuit noise; network routing; random processes; timing circuits; wires (electric); SRNR technique; induced noise; routing methodology; routing structure; semi-random net reordering; signal integrity; signal predictability; signal propagation delay; signal transition speed; timing characteristics; wide signal busses; zero cost; Couplings; Inductance; Noise; Propagation delay; Routing; Switches; Wires;
Conference_Titel :
Design and Test Workshop (IDT), 2010 5th International
Conference_Location :
Abu Dhabi
Print_ISBN :
978-1-61284-291-2
Electronic_ISBN :
978-1-61284-290-5
DOI :
10.1109/IDT.2010.5724397
