An Area Effective Parity-Based Fault Detection Technique for FPGAs

Field programmable gate arrays (FPGAs) are highly successful platforms in a variety of niches, such as telecommunications and automotive applications. Their usage in critical systems for radiation environments, however, still depends on techniques able to provide increased reliability, since such devices are susceptible to single event upsets that may alter the specified functionality. Classical approaches such as duplication with comparison and triple modular redundancy are powerful in terms of fault detection and/or correction capabilities, and can be easily applied to a variety of circuits, but come with heavy area overheads. In this work we propose a parity-based concurrent error detection technique able to provide single error detection for combinational logic in FPGAs with reduced area when compared to the classical approaches. The proposed technique is automatically applied to a set of benchmark circuits and presents an average area reduction of 24.4% when compared to duplication with comparison, with no performance overhead.