A New Algorithm for Post-Silicon Clock Measurement and Tuning

The number of speed paths in modern high-performance designs is in the range of millions. Due to unmodelled electrical effects, such as process variations and systemic delay defects, the speed paths are difficult to be measured accurately before the first silicon samples are available. To tolerate these unmodelled electrical effects, clock tuning elements are employed to aid the post-silicon clock measurement and tuning. In this paper we describe a new compute-efficient algorithm for post-silicon clock measurement and tuning, which employs smart pruning techniques that exploit the characteristics of the clock tuning buffers.