Title :
A New Algorithm for Post-Silicon Clock Measurement and Tuning
Author :
Lak, Zahra ; Nicolici, Nicola
Author_Institution :
Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, ON, Canada
Abstract :
The number of speed paths in modern high-performance designs is in the range of millions. Due to unmodelled electrical effects, such as process variations and systemic delay defects, the speed paths are difficult to be measured accurately before the first silicon samples are available. To tolerate these unmodelled electrical effects, clock tuning elements are employed to aid the post-silicon clock measurement and tuning. In this paper we describe a new compute-efficient algorithm for post-silicon clock measurement and tuning, which employs smart pruning techniques that exploit the characteristics of the clock tuning buffers.
Keywords :
clocks; silicon; tuning; Si; electrical effects; high-performance designs; post-silicon clock measurement; systemic delay defects; tuning; Algorithm design and analysis; Clocks; Delay; Frequency measurement; Tuning; Velocity measurement; Post-silicon clock tuning; configuration of clock tuning elements; setup/hold-time violations;
Conference_Titel :
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on
Conference_Location :
Vancouver, BC
Print_ISBN :
978-1-4577-1713-0
DOI :
10.1109/DFT.2011.14
