A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits

Over the last few decades, most quantitative measures of VLSI performance have improved by many orders of magnitude, this has been achieved by the unabated scaling of the sizes of MOSFETs. However, scaling also exacerbates noise and reliability issues, thus posing new challenges in circuit design. Reliability becomes a major concern due to many and often correlated factors, such as parameter variations and soft errors. Existing reliability evaluation tools focus on algorithmic development at the logic level that usually uses a constant error rate for gate failure and thus leads to approximations in the assessment of a VLSI circuit. This paper proposes a more accurate and scalable approach that utilizes a transistor-level stochastic analysis for digital fault modeling. It accounts for very detailed measures, including the probability of failure of individual transistors, the topology of logic gates, timing sequences and the applied input vectors. Simulation results are provided to demonstrate both the efficiency and the accuracy of the proposed approach.