Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits

Optimization algorithms for the synthesis of digital logic circuits have been used to automate the process of meeting design constraints like area and timing. These algorithms affect a circuit´s topology and therefore its vulnerability to soft errors. This paper investigates the impact that these optimizations have on the error propagation probability of various circuit benchmarks. Results indicate that a decrease in delay and area corresponds with an increase in error propagation probability. Additionally, an increase in mapping effort corresponds to an increase in error propagation probability.