A Schematic-Based Extraction Methodology for Dislocation Defects in Analog/Mixed-Signal Devices

This paper presents a defect extraction methodology for dislocation anomalies in analogue-mixed signal (AMS) Integrated Circuits (ICs). Dislocation defects can cross the PN junction of a transistor/diode and contribute to leakage related failures. The extraction of dislocation defects from layout information is very difficult. We propose a methodology that accepts a schematic (netlist) of the AMS design and generates a list of dislocation defects by identifying the hierarchical net names of each defect. The methodology parses the schematic (netlist) and locates dislocation defects according to pre-determined rules. The cross section of different devices from the design manual of a process technology are studied and the possible dislocation spots related to PN junctions are listed in a rule file. This methodology is applied to five AMS IC products and a considerable amount of simulation time can be saved by truncating the defect list to the extracted dislocation susceptible spots.