Title :
Parasitic memory effect in CMOS SRAMs
Author :
Irobi, Sandra ; AL-Ars, Zaid ; Renovell, Michel
Author_Institution :
CE Lab., Delft Univ. of Technol., Delft, Netherlands
Abstract :
The presence of parasitic node capacitance on a defective resistive node can induce dynamic changes in the electrical behavior of the circuit in SRAM devices, which may be referred to as the parasitic memory effect. This effect can cause dynamic faults in SRAMs. This paper presents an analysis of the parasitic memory effect in SRAMs on the defective resistive node. The paper demonstrates that the faulty behavior in SRAMs is exacerbated in the presence of parasitic node capacitance, something that reduces the fault coverage of current memory tests, and increases the defect-per-million rates.
Keywords :
CMOS memory circuits; SRAM chips; fault simulation; logic testing; CMOS SRAM; SRAM devices; current memory tests; defect-per-million rates; defective resistive node; dynamic faults; electrical behavior; fault coverage; faulty behavior; parasitic memory effect; parasitic node capacitance; Circuit faults; Delay; Integrated circuit modeling; Logic gates; Parasitic capacitance; Random access memory;
Conference_Titel :
Design and Test Workshop (IDT), 2010 5th International
Conference_Location :
Abu Dhabi
Print_ISBN :
978-1-61284-291-2
Electronic_ISBN :
978-1-61284-290-5
DOI :
10.1109/IDT.2010.5724424
