ADC architecture with direct binary output for digital controllers of high-frequency SMPS

Author

Zhou, Tao ; Xu, Jianping

Author_Institution

Dept. of Electr. Eng., Southwest Jiaotong Univ., Chengdu

Volume

2

fYear

2006

fDate

14-16 Aug. 2006

Firstpage

1

Lastpage

5

Abstract

Without adopting encoder to convert "thermometer code" into binary code, analog-to-digital converter (ADC) architecture with direct binary code output is proposed for digital controllers of high-frequency switching mode power supply (SMPS). It can provide large conversion ranges with required precision and reduce ADC circuit complexity. The output can be compressed into a much shorter addressing character in logarithmic law and lead to reduction of memory size in the look-up table of the digital compensator

Keywords

PWM power convertors; analogue-digital conversion; controllers; digital control; switched mode power supplies; table lookup; ADC architecture; analog-to-digital converter; digital compensator; digital controllers; direct binary output; high-frequency SMPS; logarithmic law; look-up table; memory size; switching mode power supply; Analog-digital conversion; Binary codes; Control systems; Delay; Digital control; Pulse width modulation; Pulse width modulation converters; Quantization; Switched-mode power supply; Voltage control; ADC; delay-line; digital controller; flash; power converter; switching mode power supply (SMPS);

fLanguage

English

Publisher

ieee

Conference_Titel

Power Electronics and Motion Control Conference, 2006. IPEMC 2006. CES/IEEE 5th International

Conference_Location

Shanghai

Print_ISBN

1-4244-0448-7

Type

conf

DOI

10.1109/IPEMC.2006.4778154

Filename

4778154