DocumentCode
2664227
Title
Coarse-grained processor array implementing the multilayer neural network model
Author
Piazza, E. ; Marchesi, M. ; Orlandi, G. ; Uncini, A.
Author_Institution
Dept. of Electron. & Autom., Ancona Univ., Italy
fYear
1990
fDate
1-3 May 1990
Firstpage
2963
Abstract
A coarse-grained processor array which tries to overcome the limitations encountered when a network composed by many neurons has to be mapped into a limited number of processing elements (PEs) is proposed. Given the total number of PEs, the proposed architecture can be configured to implement any particular multilayer perceptron (MLP) topology, and can simulate both the forward and learning phases of the network. Moreover, it has a small number of very local connections, and can exhibit a high efficiency under limited constraints on the number of neurons per layer
Keywords
learning systems; neural nets; parallel processing; coarse-grained processor array; efficiency; learning phases; local connections; multilayer neural network model; multilayer perceptron; neurons; processing elements; Artificial neural networks; Computational modeling; Computer networks; Concurrent computing; Multi-layer neural network; Network topology; Neural networks; Neurons; Parallel processing; Research and development;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112632
Filename
112632
Link To Document