A Soft Error Tolerance Estimation Method for Sequential Circuits

Author

Yoshimura, Masayoshi ; Akamine, Yusuke ; Matsunaga, Yusuke

Author_Institution

Grad. Sch. of Inf. Sci. & Electr. Eng., Kyushu Univ., Fukuoka, Japan

fYear

2011

fDate

3-5 Oct. 2011

Firstpage

268

Lastpage

276

Abstract

In advanced technology, soft error tolerance of VLSIs decreases. Soft errors might cause VLSIs to failure. However, there is no exact method to estimate soft error tolerance for sequential circuits of VLSIs. We propose an exact method to estimate soft error tolerance for sequential circuits. The failure due to soft errors in sequential circuits is defined by using the modified product machine. The behavior of the modified product machine is analyzed using Markov model strictly. We also propose two acceleration techniques to apply the exact method to larger scale circuits. Two acceleration techniques reduce the number of variables of simultaneous linear equations. We apply the proposed method to ISCAS´89 and MCNC benchmark circuits and estimate soft error tolerance for sequential circuits. Experimental results shows that two acceleration techniques reduce up to 10 times from its original execution time.

Keywords

Markov processes; VLSI; radiation hardening (electronics); sequential circuits; ISCAS´89; MCNC benchmark circuits; Markov model; VLSI; linear equations; sequential circuits; soft error tolerance estimation method; Absorption; Acceleration; Equations; Integrated circuit modeling; Mathematical model; Probability; Sequential circuits; Markov model; absorption probability; sequential circuits; soft error; soft error tolerance; the modified product machine;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on

Conference_Location

Vancouver, BC

Print_ISBN

978-1-4577-1713-0

Type

conf

DOI

10.1109/DFT.2011.22

Filename

6104452