Analysis of compressor architectures in MOS current-mode logic

Author

Caruso, Giuseppe ; Sclafani, Daniela Di

Author_Institution

Dipt. di Ing. Elettr., Elettron. e delle Telecomun., Univ. of Palermo, Palermo, Italy

fYear

2010

fDate

12-15 Dec. 2010

Firstpage

13

Lastpage

16

Abstract

This paper is concerned with the design and the comparison of different compressor architectures for high performance multipliers in MOS current-mode logic (MCML). More specifically, three architectures have been designed for 3-2, 4-2 and 5-2 compressors and two architectures for 7-2 compressors. The various implementations for each type of compressor have been compared one another. This investigation indicates that the architectures based exclusively on three-level MCML gates are the most suitable for MCML implementation in terms of speed, power consumption and area. Design guidelines are provided to improve compressor performance. All the compressors were designed in a TSMC 180nm CMOS technology.

Keywords

CMOS logic circuits; compressors; current-mode logic; CMOS technology; MOS current-mode logic; TSMC; compressor architecture; performance multipliers; power consumption; size 180 nm; three-level MCML gate; Logic gates; Compressors; MOS current-mode logic; multipliers;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Conference_Location

Athens

Print_ISBN

978-1-4244-8155-2

Type

conf

DOI

10.1109/ICECS.2010.5724442

Filename

5724442