Architecture and floorplan design techniques for video-rate FIR filters

Author

Jain, Rajeev ; Yang, Paul ; Samueli, Henry ; Yoshino, Toshiaki

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

1990

fDate

1-3 May 1990

Firstpage

3027

Abstract

Architecture and floorplan design techniques for integrated circuit finite impulse response (FIR) filters that can achieve compact layouts with sample rates in the 25-100-MHz range are described. By exploiting the design techniques described, a functional compiler called FIRGEN that can automate the entire FIR filter design from filter specifications to final chip layout was developed. The use of the transposed form with carry-save addition and CSD multipliers allows sample rates in excess of 100 MHz in 0.8-μ BiCMOS technology, and 70 MHz in 1.2-μm CMOS. By providing floorplanning constraints for the clock distribution network, the clock skew can be controlled to allow the high sample rate

Keywords

BIMOS integrated circuits; circuit CAD; digital filters; multiplying circuits; 0.8 micron; 1.2 micron; BiCMOS technology; CMOS; CSD multipliers; FIRGEN; carry-save addition; chip layout; clock distribution network; clock skew; filter specifications; finite impulse response; floorplan design techniques; functional compiler; sample rates; video-rate FIR filters; Adders; BiCMOS integrated circuits; CMOS technology; Delay; Finite impulse response filter; Integrated circuit layout; Integrated circuit technology; Laboratories; Pipeline processing; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112649

Filename

112649