• DocumentCode
    2664547
  • Title

    An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems

  • Author

    Lagos-Benites, J. ; Grosso, M. ; Reorda, M. Sonza ; Audisio, G. ; Pipponzi, M. ; Sabatini, M. ; Avantaggiati, V.A.

  • Author_Institution
    Dipt. di Autom. e Inf., Politec. di Torino, Torino, Italy
  • fYear
    2011
  • fDate
    3-5 Oct. 2011
  • Firstpage
    391
  • Lastpage
    398
  • Abstract
    Integrated transceivers play a leading role in an ever-increasing range of systems and applications where dependability is a major concern. In order to reduce time-to-market, it is crucial to verify the correctness of the hardware and software implementations and the overall system performance at early stages of the design flow with respect to specifications or a higher-level model. To this purpose, we identify some specific requirements of these systems, and propose a new methodology for early validation and BER characterization taking into consideration channel noise and sampling frequency offset of the digital base band communication subsystems. The proposed methodology is based on a low-cost FPGA platform and enables precise control of noise injection and clocking parameters during emulation, so as to reproduce channel and receiver non-ideality effects, while accelerating the validation process by orders of magnitude with respect to simulation-based alternatives. Experimental results on an industrial case consisting of the digital base band portion of an ultra-wideband wireless link confirm the effectiveness of the approach.
  • Keywords
    digital communication; error statistics; field programmable gate arrays; radio links; radio transceivers; ultra wideband communication; wireless channels; BER characterization; FPGA-emulation-based platform; channel noise; channel reproduction; design flow; digital baseband communication system; hardware and software implementation; integrated transceiver; low cost FPGA platform; noise clocking parameter; noise injection; receiver nonideality effect; sampling frequency offset; time-to-market reduction; ultrawideband wireless link; validation process; Bit error rate; Clocks; Emulation; Field programmable gate arrays; Noise; Receivers; Software; FPGA; characterization; clock frequency offset; digital baseband; noise; validation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on
  • Conference_Location
    Vancouver, BC
  • Print_ISBN
    978-1-4577-1713-0
  • Type

    conf

  • DOI
    10.1109/DFT.2011.1
  • Filename
    6104467