DocumentCode
2664555
Title
VLSI implementation of an entropy coder and decoder for advanced TV applications
Author
Lei, S.M. ; Sun, M.-T. ; Ramachandran, K. ; Palaniraj, S.
Author_Institution
Bellcore, Red Bank, NJ, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
3030
Abstract
Experimental prototype high-speed entropy coder and decoder chips with parallel architectures are discussed. Two coding techniques, run-length coding and variable-length coding, are implemented in these two chips. Designed in a 1.2-μm double-metal CMOS technology, the die-size of each chip is about 5 mm×5 mm. Each chip contains about 35 K transistors. Based on the simulation of critical parts, they are expected to meet a speed objective of 52 MHz with margin
Keywords
CMOS integrated circuits; VLSI; codecs; parallel architectures; television equipment; 1.2 micron; VLSI implementation; advanced TV applications; die-size; double-metal CMOS technology; entropy coder; entropy decoder; parallel architectures; run-length coding; speed objective; variable-length coding; CMOS technology; Decoding; Entropy; HDTV; Programmable logic arrays; Prototypes; Sampling methods; TV; Very large scale integration; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112650
Filename
112650
Link To Document