• DocumentCode
    2664560
  • Title

    Bit level processor arrays: current architectures and a design and programming tool

  • Author

    O´Keefe, Matthew T. ; Fortes, Jose A B

  • Author_Institution
    Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
  • fYear
    1988
  • fDate
    7-9 June 1988
  • Firstpage
    2751
  • Abstract
    The authors review bit-level processor arrays and the common characteristics that make them ideal for VLSI and high-speed computations. Emphasis is on arrays that have been implemented rather than proposed architectures. The essential features shared by these arrays, and those that differentiate them are characterized and used to develop a taxonomy for bit-level processor arrays. The authors also discuss programming tools, with an emphasis on RAB, a large program used to map a class of algorithms written in C onto bit-level processor arrays. The basic components and extensions to RAB are discussed. Directions of current research and design of bit-level processor array architectures and their programming environments are also briefly discussed.<>
  • Keywords
    VLSI; cellular arrays; computer architecture; software tools; C language; RAB; VLSI; array architectures; bit-level processor arrays; high-speed computations; programming environments; programming tool; taxonomy; Communication system control; Computer architecture; Concurrent computing; Hardware; Image processing; Logic arrays; Member and Geographic Activities Board committees; Parallel processing; Systolic arrays; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1988., IEEE International Symposium on
  • Conference_Location
    Espoo, Finland
  • Type

    conf

  • DOI
    10.1109/ISCAS.1988.15509
  • Filename
    15509