Low-power dual quantization-domain decoding for LDPC codes

In this paper we propose a new dual quantization-domain LDPC decoder, which requires only 3-bit messages between the check nodes and the variable nodes. To reduce complexity and save power, check nodes processing is entirely in the 3-bit domain. However, to avoid loss in performance, the variable nodes processing is in a higher bit precision domain. A non-linear mapping is used to map the messages from one quantization domain to the other. Simulations and hardware evaluation of the proposed decoder showed greater than 50% reduction in power consumption with only 0.1 dB (0.2 dB) loss in bit-error-performance when compared to a reference 5-bits scaled Min-Sum decoder over the AWGN (fading) channel.