Title :
A low-power 12-bit 2nd-order Σ-Δ analog-to-digital converter for CMOS image sensors
Author :
Yun, Gun-Hee ; Kim, Min-Kyu ; Kim, Jong-Boo ; Shin, Min-Seok ; Kwon, Oh-Kyong
Author_Institution :
Div. of Electr. & Comput. Eng., Hanyang Univ., Seoul, South Korea
Abstract :
A low-power and 12-bit resolution 2nd-order Σ-Δ ADC for CMOS image sensors is proposed. The proposed Σ-Δ ADC adopts the built-in correlated double sampling (CDS) technique and single-ended signaling to reduce the power consumption and chip area. The proposed Σ-Δ modulator of the ADC has the oversampling ratio (OSR) of 130 to achieve 12-bit resolution and the sampling rate of 1 0 M Hz to complete analog-to-digital conversion within 13 μs. The proposed ADC has been implemented using 0.35 μm 1P4M standard CMOS process. The simulation results using HSPICE show 75.8 dB SNDR and 210 μW power consumption under 2.8 V supply voltage.
Keywords :
CMOS image sensors; SPICE; circuit simulation; image processing equipment; low-power electronics; modulators; sigma-delta modulation; Σ-Δ modulator; ADC; CMOS image sensor; HSPICE; chip area; correlated double sampling technique; low power 12-bit 2nd-order Σ-Δ analog-to-digital converter; oversampling ratio; power consumption; sampling rate; single-ended signaling; size 0.35 mum; standard CMOS process; word length 12 bit; CMOS integrated circuits; Clocks; Converters; HDTV; Image resolution; Pixel; Signal resolution; Σ-Δ Modulator; Analog-Digital Converter; CMOS Image Sensor; Column-Parallel Readout; Correlated Double Sampling;
Conference_Titel :
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on
Conference_Location :
Athens
Print_ISBN :
978-1-4244-8155-2
DOI :
10.1109/ICECS.2010.5724469
