DocumentCode
2664859
Title
Synthesis for testability: a brief survey
Author
Devadas, Srinivas ; Keutzer, Kurt
Author_Institution
MIT, Cambridge, MA, USA
fYear
1990
fDate
1-3 May 1990
Firstpage
3097
Abstract
Previously published work in the synthesis and testing areas is briefly surveyed and critically discussed. Synthesis for testability for both combinational logic and sequential circuits is discussed
Keywords
combinatorial circuits; logic design; logic testing; sequential circuits; combinational logic; design for testability; sequential circuits; synthesis for testability; testing; Adders; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Delay; Logic testing; Redundancy; Robustness; Sufficient conditions;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/ISCAS.1990.112667
Filename
112667
Link To Document