Synthesis of combinational logic circuits for path delay fault testability

An approach to the design of multilevel, multi-output combinational logic circuits in which all path delay faults are detectable by robust tests is proposed. Inadequacies of previous approaches for synthesis for testability of path delay faults are discussed. A necessary and sufficient condition for the existence of a hazard-free robust test for a path is stated. Violation of this condition is adopted as the criterion for identifying the paths, in a given circuit, which are not testable by hazard-free robust tests. Transformation methods to render these paths testable are proposed