Title :
Low-area tunable CMOS resistor with improved linearity
Author_Institution :
Fac. of Electron., Telecommun. & Inf. Technol., Univ. Politeh. of Bucharest, Bucharest, Romania
Abstract :
A new linearity improvement technique for a CMOS active resistor will be presented. In order to minimize the silicon area, an original method based on an optimal implementation of the current-controlled voltage generator will be proposed. The circuit is implemented in 0.35μm CMOS technology on a die area of 25μm × 40μm, being supplied at ± 3.6V. The active resistor presents a very good linearity (THD <; 0.75%) for an extended range of the input voltage (-1.8V <; VX - VY <; 1.8V). The tuning range is extremely large comparing with the previous reported active resistors: ± (300kΩ - 3MΩ), the circuit being able to simulate both positive and negative active resistances.
Keywords :
CMOS integrated circuits; resistors; active resistance; current-controlled voltage generator; linearity improvement technique; low-area tunable CMOS active resistor; resistance -300 kohm to -3 Mohm; resistance 300 kohm to 3 Mohm; size 0.35 mum; voltage -3.6 V; voltage 3.6 V; BiCMOS integrated circuits; CMOS integrated circuits; CMOS technology; Complexity theory; Low voltage; Resistance; Resistors; active resistor; complexity; linearity error; silicon area;
Conference_Titel :
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on
Conference_Location :
Athens
Print_ISBN :
978-1-4244-8155-2
DOI :
10.1109/ICECS.2010.5724486
