DocumentCode
2665334
Title
Testing wafer scale arrays: constant testability under multiple faults
Author
Sciuto, D. ; Lombardi, F.
Author_Institution
Dept. of Ind. Autom., Brescia Univ., Italy
fYear
1990
fDate
23-25 Jan 1990
Firstpage
251
Lastpage
257
Abstract
Deals with the testing of one-dimensional arrays in a complexity independent of array size (C-testability). The first aspect of C-testability analyzed in this paper, is a new model for the internal organization of a basic cell under a restricted fault assumption. This paper also presents a new approach for multiple fault detection of one-dimensional (linear) arrays
Keywords
VLSI; cellular arrays; integrated circuit technology; integrated circuit testing; parallel architectures; C-testability; WSI; complexity independent of array size; internal organization; linear arrays; multiple fault detection; one-dimensional arrays; restricted fault assumption; Automatic testing; Automation; Computer industry; Computer science; Fault detection; Logic arrays; Manufacturing; Production; System testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-8186-9013-5
Type
conf
DOI
10.1109/ICWSI.1990.63908
Filename
63908
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