A NoC-based multi-{soft}core with 16 cores

Author

Fernandez-Alonso, Eduard ; Castells-Rufas, David ; Risueno, Sergi ; Carrabina, Jordi ; Joven, Jaume

Author_Institution

CEPHIS, Univ. Autonoma de Barcelona, Barcelona, Spain

fYear

2010

fDate

12-15 Dec. 2010

Firstpage

259

Lastpage

262

Abstract

The number of resources available in the largest reconfigurable devices enables the synthesis of systems with more than 100 Soft-Core processors. Although a feasible and attainable option, few such systems have been built and few published works propose methods to create, program and optimize this kind of system. In this work we present a methodology that helps the designer to build Multi Processor System on Chip (MPSoC) systems based on Network on Chip (NoC) interconnection, and also to develop applications and to analyze their performance. In this methodology several tools have been combined such as SOPC builder from Altera, NoCMaker from UAB, and Vampir from GWT-TUD. As a result, a NoC-based MPSoC consisting of 16 NIOS II Soft-Core processors has been built and successfully tested with several applications.

Keywords

microprocessor chips; multiprocessor interconnection networks; network-on-chip; parallel programming; NoCMaker; SOPC builder; Vampir; multiprocessor system on chip system; network on chip interconnection; soft-core processor; Large scale integration; Mixers; Scalability; FPGA; MPI; MPSoC; NoC; Parallel programming; Performance analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Conference_Location

Athens

Print_ISBN

978-1-4244-8155-2

Type

conf

DOI

10.1109/ICECS.2010.5724503

Filename

5724503