High-frequency broadband amplifier ASIC design optimization using pole-zero compensation techniques

Author

Mercer, Mark J. ; Burns, Stanley G.

Author_Institution

Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA

fYear

1990

fDate

1-3 May 1990

Firstpage

3225

Abstract

The relative performance of a hierarchy of broadband amplifier designs is examined. This design hierarchy consists of an emitter-coupled pair with resistive-shunt loading for baseline comparison, a compound-device amplifier, a compensated series-feedback amplifier, and an actively shunt-peaked amplifier. Both pole-zero compensated amplifiers incorporate compound devices. The circuits are fabricated on Tektronix Inc.´s analog array chip featuring the SH3 process with 6.5 f_T transistors

Keywords

application specific integrated circuits; compensation; feedback; high-frequency amplifiers; linear integrated circuits; poles and zeros; radiofrequency amplifiers; wideband amplifiers; ASIC design optimization; SH3 process; Tektronix; UHF; VHF; actively shunt-peaked amplifier; analog array chip; broadband amplifier; compensated series-feedback amplifier; compound-device amplifier; emitter-coupled pair; monolithic IC; pole-zero compensation techniques; resistive-shunt loading; Application specific integrated circuits; Bandwidth; Broadband amplifiers; Design optimization; Frequency; Impedance; Integrated circuit modeling; Performance gain; Predictive models; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112698

Filename

112698