FPGA-Based Image Processor Architecture for Wireless Multimedia Sensor Network

This paper presents the architecture of a FPGA-based efficient processing system suited to Wireless Multimedia Sensor Networks. The core is a 16-bit RISC microprocessor, which is designed to operate at low frequency and is optimized for handling instructions and operations of the Wireless Sensor Networks. A part of the processor is empowered with image processing functions, optimized for handling image processing instructions and operates at high frequency. The image processing function of the processor is optimized to achieve high speed processing with minimal hardware and power consumption. Experiments have been conducted to verify the image compression and transmission ability of the proposed design and to investigate other WMSN issues such as image packetization, power management and system synchronization. These experiments reveal that the proposed approach is suitable for WMSN applications and removes a many issues associated with using off-the-shelf processors.