Title :
Logical function and delay time extraction from MOS circuit data
Author :
Fujiyoshi, Kunihiro ; Kaneko, Mineo ; Onoda, Mahoki
Author_Institution :
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
Abstract :
An algorithm to extract logical function and delay-time from CMOS circuit-level data is proposed. The resultant data from this algorithm is a logic-level circuit description. It is applied to conventional logic simulators. As a result, a large circuit can be simulated at once, and the time needed for simulation and verification is saved. The algorithm consists of three parts, network partitioning, extraction of logical function, and extraction of delay time
Keywords :
CMOS integrated circuits; circuit analysis computing; delays; integrated logic circuits; logic CAD; CAD; CMOS circuit-level data; MOS circuit data; delay time extraction; large circuit; logic simulators; logic-level circuit description; logical function; network partitioning; CMOS logic circuits; Circuit simulation; Computational modeling; Data mining; Delay effects; Logic circuits; MOSFETs; Partitioning algorithms; Timing; Variable structure systems;
Conference_Titel :
Circuits and Systems, 1990., IEEE International Symposium on
Conference_Location :
New Orleans, LA
DOI :
10.1109/ISCAS.1990.112701
