Title :
A new low-power and low-complexity all digital PLL (ADPLL) in 180nm and 32nm
Author :
Abadian, Arash ; Lotfizad, Mojtaba ; Majd, Nasser Erfani ; Ghoushchi, Mohammad Bagher Ghaznavi ; Mirzaie, Hossein
Author_Institution :
Dept. of Electr. & Comput. Eng., Tarbiat Modares Univ. (TMU), Tehran, Iran
Abstract :
In this paper, an all digital phase locked loop is proposed. The proposed ADPLL uses counter for locking the output signal. The proposed circuit has a simple structure in locking mechanism, and the power consumption of this design is very low. The proposed design is evaluated in TSMC 180nm and PTM 32nm. The power consumption of the proposed ADPLL for 180nm, at 403 MHz frequency is 2.5mW and in 32nm at 720MHz is 1.33 mW. Two novel blocks are introduced for glitch removing in ADPLL and any other digital circuit. The reduction of glitches also affects on low power design. The digitally controlled oscillator (DCO) used here is based on ring oscillators with fine and coarse bits applied on it. The DCO achieves very high resolution with 0.1 ps due to 16-bit control code.
Keywords :
digital phase locked loops; low-power electronics; oscillators; all digital phase locked loop; digital circuit; digitally controlled oscillator; frequency 403 MHz; frequency 720 MHz; locking mechanism; low power design; low-power all digital PLL; power 2.5 mW; power consumption; size 180 nm; size 32 nm; time 0.1 ps; Delay; Frequency conversion; Logic gates; Signal resolution; all digital phase locked loop (ADPLL); digitally controlled oscillator (DCO); jitter; phase frequency detector (PFD);
Conference_Titel :
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on
Conference_Location :
Athens
Print_ISBN :
978-1-4244-8155-2
DOI :
10.1109/ICECS.2010.5724514
