A modified Rijndael algorithm and it´s implementation using FPGA

Author

Mohamed, Ahmed A. ; Madian, Ahmed H.

Author_Institution

Electr. & Electron. Eng. Dept., German Univ. in Cairo, Cairo, Egypt

fYear

2010

fDate

12-15 Dec. 2010

Firstpage

335

Lastpage

338

Abstract

Cryptography algorithms are becoming more necessary to ensure secure data transmission, which can be used in several applications. A modified Rijndael algorithm capable of encrypting a 128 bit input/output/key is presented. The presented algorithm depends on substitution and permutation network (SP-Network) rather than feistel network. A new stage is proposed in the encryption process. The introduced architecture was implemented by VHDL, schematic and core generator - Based Design which are synthesized, placed and routed in Virtex XCV800-6bg432 which resulted in an optimized area (7148) slices and (44) MHz clock speed. Post simulations for major functions and the final algorithm are presented and discussed.

Keywords

cryptography; field programmable gate arrays; hardware description languages; FPGA; VHDL; Virtex XCV800-6bg432; core generator based design; cryptography algorithms; encryption process; frequency 44 MHz; modified Rijndael algorithm; schematic generator based design; secure data transmission; substitution and permutation network; Encryption; Indium phosphide; AES; Encryption; Rijndael; Security; cryptography;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Conference_Location

Athens

Print_ISBN

978-1-4244-8155-2

Type

conf

DOI

10.1109/ICECS.2010.5724521

Filename

5724521