A low-voltage current sorting circuit based on 4-T min-max CMOS switch

A low-voltage, compact and fast circuit for sorting currents is reported. It is based on an enhanced four-transistor (4-T) min-max CMOS switch to reduce the switch voltage drop. The inherent avoidance of mirroring that produces mismatch is extended to the whole sorting circuit, while keeping the voltage drop to very low levels. The sorted output currents are by construction equal to the input currents, so errors can be greatly reduced compared to other approaches. Simulations show that, for a 0.35 μm technology, a three-stage cascade operates correctly at V_DD = 1.2 V, being each stage voltage drop tens of mV.