An efficient approach to test verification for VLSI circuits

A novel fault-detection scheme, called DRC (delay redundancy check), is proposed. This scheme is designed to be combined with VRC and HRC (vertical and horizontal redundancy check) to achieve a high fault coverage. The minimum distance is increased by two, and delay elements are used to skew the outputs in time. The lost fault coverage of the test verification scheme VRC+HRC+DRC is calculated as one out of 2^5n-8×m⁴ for an n-input and m-output CUT (circuit under test). Using the two-signature approach for the data compaction of the output sequences of VRC+HRC and DRC, the frequency of fault masking is reduced to one in 2⁴ⁿ for an n-input and m-output CUT, where 2ⁿ>m