An efficient approach to test verification for VLSI circuits

Author

Chen, Chien-In Henry

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

fYear

1990

fDate

21-25 May 1990

Firstpage

47

Abstract

A novel fault-detection scheme, called DRC (delay redundancy check), is proposed. This scheme is designed to be combined with VRC and HRC (vertical and horizontal redundancy check) to achieve a high fault coverage. The minimum distance is increased by two, and delay elements are used to skew the outputs in time. The lost fault coverage of the test verification scheme VRC+HRC+DRC is calculated as one out of 2^5n-8×m⁴ for an n-input and m-output CUT (circuit under test). Using the two-signature approach for the data compaction of the output sequences of VRC+HRC and DRC, the frequency of fault masking is reduced to one in 2⁴ⁿ for an n-input and m-output CUT, where 2ⁿ>m

Keywords

VLSI; built-in self test; fault location; integrated circuit testing; redundancy; BIST; IC testing; VLSI circuits; data compaction; delay redundancy check; fault coverage; fault masking; fault-detection; horizontal redundancy check; test generation; test verification; two-signature; vertical redundancy check; Algorithm design and analysis; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Hardware; Partitioning algorithms; Signal design; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace and Electronics Conference, 1990. NAECON 1990., Proceedings of the IEEE 1990 National

Conference_Location

Dayton, OH

Type

conf

DOI

10.1109/NAECON.1990.112738

Filename

112738