Title :
Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth
Author :
Bracy, Anne ; Prahlad, Prashant ; Roth, Amir
Author_Institution :
University of Pennsylvania
Abstract :
A mini-graph is a dataflow graph that has an arbitrary internal size and shape but the interface of a singleton instruction: two register inputs, one register output, a maximum of one memory operation, and a maximum of one (terminal) control transfer. Previous work has exploited dataflow sub-graphs whose execution latency can be reduced via programmable FPGA-style hardware. In this paper we show that mini-graphs can improve performance by amplifying the bandwidths of a superscalar processor´s stages and the capacities of many of its structures without custom latency-reduction hardware. Amplification is achieved because the processor deals with a complete mini-graph via a single quasi-instruction, the handle. By constraining mini-graph structure and forcing handles to behave as much like singleton instructions as possible, the number and scope of the modifications over a conventional superscalar microarchitecture is kept to a minimum. This paper describes mini-graphs, a simple algorithm for extracting them from basic block frequency profiles, and a microarchitecture for exploiting them. Cycle-level simulation of several benchmark suites shows that mini-graphs can provide average performance gains of 2-12% over an aggressive baseline, with peak gains exceeding 40%. Alternatively, they can compensate for substantial reductions in register file and scheduler size, and in pipeline bandwidth.
Keywords :
Bandwidth; Delay; Frequency; Hardware; Microarchitecture; Performance gain; Pipelines; Registers; Shape control; Size control;
Conference_Titel :
Microarchitecture, 2004. MICRO-37 2004. 37th International Symposium on
Print_ISBN :
0-7695-2126-6
DOI :
10.1109/MICRO.2004.15