Title :
Sampled data analog signal processor
Author :
Jundi, Khaled ; Siferd, Ray
Author_Institution :
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
Abstract :
A CMOS integrated circuit implementation of a sampled data analog signal processor which incorporates four-quadrant analog multipliers as a key component is presented. The four-quadrant multiplier facilitates signed analog inputs for both data and transfer function coefficients and thereby provides the same flexibility as digital processors for programmable and adaptive applications. Unique architectural features include a parallel configuration for the sample-and-hold circuit and a capacitor summing circuit. The processor was fabricated in a 2-micron double-poly, double-metal process
Keywords :
CMOS integrated circuits; linear integrated circuits; multiplying circuits; parallel architectures; sample and hold circuits; signal processing equipment; summing circuits; transfer functions; 2 micron; CMOS integrated circuit; adaptive applications; capacitor summing circuit; double metal process; double poly process; four-quadrant analog multipliers; parallel configuration; programmable application; sample-and-hold circuit; sampled data analog signal processor; transfer function coefficients; CMOS analog integrated circuits; CMOS process; Capacitors; Clocks; Finite impulse response filter; Operational amplifiers; Sampling methods; Signal processing; Summing circuits; Transfer functions;
Conference_Titel :
Aerospace and Electronics Conference, 1990. NAECON 1990., Proceedings of the IEEE 1990 National
Conference_Location :
Dayton, OH
DOI :
10.1109/NAECON.1990.112741
