Title :
LOCOS CMOS process simulation
Author :
Andriukait, Darius ; Anilionis, Romualdas ; Kersys, Tomas
Author_Institution :
Dept. of Electron. Eng., Kaunas Univ. of Technol.
Abstract :
Problems of process LOCOS, related with oxidation time, temperature, silicon oxide layer, patterned silicon nitride in CMOS structure was researched. Most CMOS quality depends on gate channel shortening, diffusion region separation during LOCOS. LOCOS CMOS mathematical models are created using program SUPREM. It is determined, that channel length almost changeless when process time t=360 min., temperature T=1000 degC, SiO2 thickness =20 nm, Si3 N4 thickness=100 nm
Keywords :
CMOS integrated circuits; integrated circuit modelling; oxidation; semiconductor process modelling; silicon compounds; 100 nm; 1000 C; 20 nm; 360 min; CMOS process simulation; LOCOS process; SUPREM program; Si3N4; SiO2; diffusion region; gate channel shortening; mathematical models; oxidation time; silicon nitride; silicon oxide layer; CMOS process; CMOS technology; Dielectrics; Fabrication; Isolation technology; MOSFETs; Oxidation; Production; Silicon; Temperature;
Conference_Titel :
Information Technology Interfaces, 2006. 28th International Conference on
Conference_Location :
Cavtat/Dubrovnik
Print_ISBN :
953-7138-05-4
DOI :
10.1109/ITI.2006.1708530
