A single-chip pipelined 2-D FIR filter using residue arithmetic

The authors present novel circuits for residue arithmetic, which have been configured to form a 3×3 finite impulse response (FIR) filter with programmable coefficients. The filter has a pipelined architecture and includes testability in the form of scan path. Area efficient circuits for residue adders, subtractors, and binary-to-residue converters have been designed. An encoding scheme has been used to reduce the residue multiplier area. A tree architecture for residue-to-binary conversion has been developed. The filter is timed with a two-phase clock, which has an estimated frequency of 15 MHz