• DocumentCode
    2666152
  • Title

    Dynamically Controlled Resource Allocation in SMT Processors

  • Author

    Cazorla, Francisco J. ; Ramirez, Alex ; Valero, Mateo ; Fernández, Enrique

  • Author_Institution
    Universitat Politècnica de Catalunya, Spain
  • fYear
    2004
  • fDate
    04-08 Dec. 2004
  • Firstpage
    171
  • Lastpage
    182
  • Abstract
    SMT processors increase performance by executing instructions from several threads simultaneously. These threads use the resources of the processor better by sharing them but, at the same time, threads are competing for these resources. The way critical resources are distributed among threads determines the final performance. Currently, processor resources are distributed among threads as determined by the fetch policy that decides which threads enter the processor to compete for resources. However, current fetch policies only use indirect indicators of resource usage in their decision, which can lead to resource monopolization by a single thread or to resource waste when no thread can use them. Both situations can harm performance and happen, for example, after an L2 cache miss. In this paper, we introduce the concept of dynamic resource control in SMT processors. Using this concept, we propose a novel resource allocation policy for SMT processors. This policy directly monitors the usage of resources by each thread and guarantees that all threads get their fair share of the critical shared resources, avoiding monopolization. We also define a mechanism to allow a thread to borrow resources from another thread if that thread does not require them, thereby reducing resource under-use. Simulation results show that our dynamic resource allocation policy outperforms a static resource allocation policy by 8%, on average. It also improves the best dynamic resource-conscious fetch policies like FLUSH++ by 4%, on average, using the harmonic mean as a metric. This indicates that our policy does not obtain the ILP boost by unfairly running high ILP threads over slow memory-bounded threads. Instead, it achieves a better throughput-fairness balance.
  • Keywords
    Computer aided instruction; Microarchitecture; Operating systems; Process control; Processor scheduling; Resource management; Surface-mount technology; Throughput; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microarchitecture, 2004. MICRO-37 2004. 37th International Symposium on
  • ISSN
    1072-4451
  • Print_ISBN
    0-7695-2126-6
  • Type

    conf

  • DOI
    10.1109/MICRO.2004.17
  • Filename
    1550992