DocumentCode :
2666170
Title :
Conjoined-Core Chip Multiprocessing
Author :
Kumar, Rakesh ; Jouppi, Norman P. ; Tullsen, Dean M.
Author_Institution :
University of California, San Diego
fYear :
2004
fDate :
04-08 Dec. 2004
Firstpage :
195
Lastpage :
206
Abstract :
Chip Multiprocessors (CMP) and Simultaneous Multi-threading (SMT) are two approaches that have been proposed to increase processor efficiency. We believe these two approaches are two extremes of a viable spectrum. Between these two extremes, there exists a range of possible architectures, sharing varying degrees of hardware between processors or threads. This paper proposes conjoined-core chip multiprocessing - topologically feasible resource sharing between adjacent cores of a chip multiprocessor to reduce die area with minimal impact on performance and hence improving the overall computational efficiency. It investigates the possible sharing of floating-point units, crossbar ports, instruction caches, and data caches and details the area savings that each kind of sharing entails. It also shows that the negative impact on performance due to sharing is significantly less than the benefits of reduced area. Several novel techniques for intelligent sharing of the hardware resources to minimize performance degradation are presented.
Keywords :
Computer architecture; Computer science; Costs; Hardware; Milling machines; Multithreading; Process design; Resource management; Surface-mount technology; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microarchitecture, 2004. MICRO-37 2004. 37th International Symposium on
ISSN :
1072-4451
Print_ISBN :
0-7695-2126-6
Type :
conf
DOI :
10.1109/MICRO.2004.12
Filename :
1550994
Link To Document :
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